 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| LTC1343 Software-Selectable Multiprotocol Transceiver FEATURES s DESCRIPTIO s s s s s Software-Selectable Transceiver Supports: RS232, RS449, EIA-530, EIA-530-A, V.35, V.36, X.21 NET1 and NET2 Compliant Software-Selectable Cable Termination Using the LTC1344 4-Driver/4-Receiver Configuration Provides a Complete 2-Chip DTE or DCE Port Operates from Single 5V Supply Internal Echoed Clock and Loop-Back Logic APPLICATIO S s s s Data Networking CSU and DSU Data Routers , LTC and LT are registered trademarks of Linear Technology Corporation. The LTC(R)1343 is a 4-driver/4-receiver multiprotocol transceiver that operates from a single 5V supply. Two LTC1343s form the core of a complete software-selectable DTE or DCE interface port that supports the RS232, RS449, EIA-530, EIA-530-A, V.35, V.36 or X.21 protocols. Cable termination may be implemented using the LTC1344 software-selectable cable termination chip or by using existing discrete designs. The LTC1343 runs from a single 5V supply using an internal charge pump that requires only five space saving surface mount capacitors. The mode pins are latched internally to allow sharing of the select lines between multiple interface ports. Software-selectable echoed clock and loop-back modes help eliminate the need for external glue logic between the serial controller and line transceiver. The part features a flowthrough architecture to simplify EMI shielding and is available in the 44-lead SSOP surface mount package. TYPICAL APPLICATIO CTS DSR DCD DTE Multiprotocol Serial Interface with DB-25 Connector DTR RTS RL TM RXD RXC TXC SCTE TXD LL LTC1343 D4 R4 R3 R2 R1 D3 D2 D1 R4 R3 R2 LTC1343 D4 R1 D3 D2 D1 13 5 22 6 10 8 23 20 19 4 21 1 7 25 16 3 9 17 12 15 11 24 14 2 DB-25 CONNECTOR U LTC1344 18 U U DSR B DSR A (107) RL A (140) CTS B CTS A (106) DTR B DTR A (108) RTS B RTS A (105) SHIELD (101) SGND (102) TM A (142) RXD B RXD A (104) RXC B RXC A (115) DCD B DCD A (109) SCTE B SCTE A (113) TXD B TXD A (103) LL A (141) TXC B TXC A (114) 1343 TA01 1 LTC1343 ABSOLUTE MAXIMUM RATINGS (Note 1) PACKAGE/ORDER INFORMATION TOP VIEW VDD C1+ PWRVCC C1- D1 D2 D3 VCC D4 1 2 3 4 5 6 7 8 9 D3 D2 D1 CHARGE PUMP 44 C2 + 43 C2 - 42 VEE 41 PGND 40 GND 39 D1 A 38 D2 A 37 D2 B 36 D3 A 35 D3 B 34 D4 A D4 33 D4 B 32 R1 A R1 31 R1 B 30 R2 A R2 29 R2 B 28 R3 A R3 27 R3 B 26 R4 A 25 423 SET 24 EC 23 LB GW PACKAGE 44-LEAD PLASTIC SSOP Supply Voltage ....................................................... 6.5V Input Voltage Transmitters ........................... - 0.3V to (VCC + 0.3V) Receivers ............................................... - 18V to 18V Logic Pins .............................. - 0.3V to (VCC + 0.3V) Output Voltage Transmitters ................. (VEE - 0.3V) to (VDD + 0.3V) Receivers ................................ - 0.3V to (VCC + 0.3V) Logic Pins .............................. - 0.3V to (VCC + 0.3V) VEE ........................................................ - 10V to 0.3V VDD ....................................................... - 0.3V to 10V Short-Circuit Duration Transmitter Output ..................................... Indefinite Receiver Output .......................................... Indefinite VEE .................................................................. 30 sec Operating Temperature Range LTC1343C .............................................. 0C to 70C LTC1343I ........................................... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C ORDER PART NUMBER LTC1343CGW LTC1343IGW D4EN 10 INVERT 11 R1EN 12 R1O 13 R2O 14 R3O 15 R4O 16 M0 17 M1 18 M2 19 CTRL/CLK 20 DCE/DTE 21 LATCH 22 R4 TJMAX = 150C, JA = 65C/ W Consult factory for Military grade parts. The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V (Notes 2, 3) SYMBOL Supplies ICC VCC Supply Current (DCE Mode, All Digital Pins = GND or VCC) V.10 Mode, No Load V.10 Mode, Full Load RS530, RS530-A, X.21 Modes, No Load RS530, RS530-A, X.21 Modes, Full Load V.35 Mode, No Load V.35 Mode, Full Load V.28 Mode, No Load V.28 Mode, Full Load No-Cable Mode V.10 Mode, Full Load RS530, RS530-A, X.21 Modes, Full Load V.35 Mode, Full Load V.28 Mode, Full Load Any Mode, No Load V.28 Mode, with Load V.28 Mode, Full Load V.35 Mode, Full Load - 40C TA 85C V.10, RS530, RS530A, X.21 Modes, Full Load - 40C TA 85C q q q q q q q q q q q q ELECTRICAL CHARACTERISTICS PARAMETER CONDITIONS MIN TYP 12 80 80 160 20 115 20 30 0.05 400 680 500 150 MAX UNITS mA mA mA mA mA mA mA mA mA mW mW mW mW V V V V V V V 150 200 160 90 1 PD Internal Power Dissipation (DCE Mode, All Digital Pins = GND or VCC) V+ V- Positive Charge Pump Output Voltage Negative Charge Pump Output Voltage 8.5 8.0 - 7.8 - 5.8 - 5.5 - 5.0 - 4.8 9.1 7.0 - 8.4 - 6.7 - 6.1 2 U W U U WW W LTC1343 The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V (Notes 2, 3) SYMBOL tr VIH VIL IIN VOH VOL IOSR IOZR V.11 Driver VOD VOD VOC VOC ISS IOZ t r, t f t PLH t PHL t t SKEW VTH VTH IIN RIN t r, t f t PLH Differential Output Voltage Open Circuit, RL = 1.95k RL = 50 (Figure 1), VOD at 50 > 1/2 VOD at RL = 1.95k RL = 50 (Figure 1) RL = 50 (Figure 1) RL = 50 (Figure 1) - 0.25V VO 0.25V, Power Off or No-Cable Mode or Driver Disabled - 0.25V VO 0.25V, Power Off or No-Cable Mode or Driver Disabled (Figures 2, 6) (Figures 2, 6), 0C TA 70C (Figures 2, 6), - 40C TA 85C (Figures 2, 6), 0C TA 70C (Figures 2, 6), - 40C TA 85C (Figures 2, 6), 0C TA 70C (Figures 2, 6), - 40C TA 85C (Figures 2, 6) - 7V VCM 7V, 0C TA 70C - 7V VCM 7V, - 40C TA 85C - 7V VCM 7V, 0C TA 70C - 7V VCM 7V, - 40C TA 85C - 10V VA, B 10V - 10V VA, B 10V (Figures 2, 7) (Figures 2, 7), CTRL = GND, 0C TA 70C CTRL = VCC, 0C TA 70C (Figures 2, 7), CTRL = GND, - 40C TA 85C CTRL = VCC, - 40C TA 85C q q q q q q q q q q q q q q q q q q q q q ELECTRICAL CHARACTERISTICS PARAMETER Supply Rise Time Logic Input High Voltage Logic Input Low Voltage Logic Input Current Output High Voltage Output Low Voltage Output Short-Circuit Current Three-State Output Current CONDITIONS No-Cable Mode or Power-Up to Turn On q q q MIN TYP 2 MAX UNITS ms V Logic Inputs and Outputs 2 0.8 10 3 - 60 - 70 1 6 4.5 0.3 0.8 60 70 V A V V mA mA A V V V V V mA A ns ns ns ns ns ns ns ns 0.2 0.3 15 40 60 0.50 20 35 25 32 15 80 400 80 400 115 130 V V mV mV mA k ns ns ns ns ns IO = - 4mA IO = 4mA 0V VO VCC, 0C TA 70C 0V VO VCC, - 40C TA 85C M0 = M1 = M2 = VCC, 0V VO VCC q q q q 2 Change in Magnitude of Differential Output Voltage Common Mode Output Voltage Change in Magnitude of Common Mode Output Voltage Short-Circuit Current Output Leakage Current Rise or Fall Time Input to Output Input to Output Input to Output Difference, tPLH - tPHL Output to Output Skew Input Threshold Voltage Input Hysteresis Input Current (A, B) Input Impedance Rise or Fall Time Input to Output 0.2 3.0 0.2 150 0.01 4 25 25 25 25 0 0 13 55 55 55 55 3 3 3 - 0.2 - 0.3 100 25 80 90 80 90 17 25 V.11 Receiver 3 LTC1343 The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V (Notes 2, 3) SYMBOL t PHL PARAMETER Input to Output CONDITIONS (Figures 2, 7), CTRL = GND, 0C TA 70C CTRL = VCC, 0C TA 70C (Figures 2, 7), CTRL = GND, -40C TA 85C CTRL = VCC, -40C TA 85C t V.35 Driver VOD IOH IOL IOZ t r , tf t PLH t PHL t t SKEW VTH VTH IIN RIN t r, t f tPLH tPHL t V.10 Driver VO Output Voltage Open Circuit, RL = 3.9k RL = 450 (Figure 4) VO at 450 > 0.9 VO at RL = 3.9k Driver 1 Only VO = GND; EIA-530, X.21, EIA-530-A Modes - 0.25V VO 0.25V, Power Off or No-Cable Mode or Driver Disabled (Figures 4, 8), RL = 450, CL = 100pF R423SET = 100k (Figures 4, 8), RL = 450, CL = 100pF R423SET = 100k (Figures 4, 8), RL = 450, CL = 100pF R423SET = 100k q q q q q ELECTRICAL CHARACTERISTICS MIN 35 25 0 0 TYP 80 400 80 400 5 5 MAX 115 130 17 25 6.0 0.66 - 9.4 12.6 100 75 90 75 90 17 25 UNITS ns ns ns ns ns ns V V mA mA A ns ns ns ns ns ns ns ns Input to Output Difference, tPLH - tPHL (Figures 2, 7), 0C TA 70C (Figures 2, 7), -40C TA 85C Open Circuit With Load, - 4.0V VCM = 4.0V (Figure 3) VA, B = 0V VA, B = 0V - 0.25V VA, B 0.25V (Figures 3, 6) (Figures 3, 6), 0C TA 70C (Figures 3, 6), -40C TA 85C (Figures 3, 6), 0C TA 70C (Figures 3, 6), -40C TA 85C (Figures 3, 6), 0C TA 70C (Figures 3, 6), -40C TA 85C (Figures 3, 6) - 2V (VA + VB)/2 2V (Figure 3) - 2V (VA + VB)/2 2V (Figure 3) - 10V VA, B 10V - 10V VA, B 10V (Figures 3, 7) (Figures 3, 7), 0C TA 70C (Figures 3, 7), -40C TA 85C (Figures 3, 7), 0C TA 70C (Figures 3, 7), -40C TA 85C (Figures 3, 7), 0C TA 70C (Figures 3, 7), -40C TA 85C Differential Output Voltage Transmitter Output High Current Transmitter Output Low Current Transmitter Output Leakage Current Rise or Fall Time Input to Output Input to Output Input to Output Difference, tPLH - tPHL Output to Output Skew Differential Receiver Input Threshold Voltage Receiver Input Hysteresis Receiver Input Current (A, B) Receiver Input Impedance Rise or Fall Time Input to Output Input to Output Input to Output Difference, tPLH - tPHL q q q q 0.44 - 12.6 9.4 0.55 - 11 11 0.01 5 q q q q q q 25 25 25 25 0 0 45 45 45 45 5 5 4 V.35 Receiver q q q q - 0.2 11 20 32 15 80 80 100 100 4 4 4.0 3.6 0.2 40 0.50 V mV mA k ns q q q q q q 115 130 115 130 17 25 6.0 ns ns ns ns ns ns V V ISS IOZ t r, t f t PLH t PHL Short-Circuit Current Output Leakage Current Rise or Fall Time Input to Output Input to Output 150 0.1 100 mA A 4 8 8 s s s 4 LTC1343 The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V (Notes 2, 3) SYMBOL VTH VTH IIN RIN t r, t f t PLH t PHL V.28 Driver VO ISS IOZ SR t PLH t PHL VTHL VTLH VTH RIN t r, tf tPLH tPHL Output Voltage Short-Circuit Current Output Leakage Current Slew Rate Input to Output Input to Output Input Low Threshold Voltage Input High Threshold Voltage Receiver Input Hysteresis Receiver Input Impedance Rise or Fall Time Input to Output Input to Output - 15V VA 15V (Figures 5, 9) (Figures 5, 9), CTRL = 0V CTRL = VCC (Figures 5, 9), CTRL = 0V CTRL = VCC q q ELECTRICAL CHARACTERISTICS PARAMETER Receiver Input Threshold Voltage Receiver Input Hysteresis Receiver Input Current Receiver Input Impedance Rise or Fall Time Input to Output Input to Output CONDITIONS 0C TA 70C -7V VCM 7V, - 40C TA 85C - 10V VA 10V - 10V VA 10V (Figures 5, 9) (Figures 5, 9) (Figures 5, 9) Open Circuit RL = 3k (Figure 4) VO = GND - 0.25V VO 0.25V, Power Off or No-Cable Mode or Driver Disabled (Figures 4, 8), RL = 3k, CL = 2500pF (Figures 4, 8), RL = 3k, CL = 2500pF (Figures 4, 8), RL = 3k, CL = 2500pF q q q q q MIN - 0.2 - 0.3 TYP MAX 0.2 0.3 UNITS V V mV mA k ns ns ns V.10 Receiver 11 20 30 15 350 350 50 0.50 q q q q q q 5 10 7.6 150 0.01 100 30.0 1.6 1.6 1.4 2.5 2.5 0.8 1.0 7 V V mA A V/s s s V V V k ns ns ns ns ns 4.0 V.28 Receiver q q q q 2.0 0.1 3 1.4 0.4 5 15 110 330 170 480 800 800 Note 1: Absolute Maximum Ratings are those beyond which the safety of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of device are negative. All voltages are referenced to device ground unless otherwise specified. Note 3: All typicals are given for VCC = 5V, C1 = C2 = CVCC = CVDD = 1F, CVEE = 3.3F tantalum capacitors and TA = 25C. PIN FUNCTIONS VDD (Pin 1): Generated Positive Supply Voltage for RS232. Connect a 1F capacitor to ground. C1 + (Pin 2): Capacitor C1 Positive Terminal. Connect a 1F capacitor between C1 + and C1 -. PWRVCC (Pin 3): Positive Supply for the Charge Pump. 4.75V PWRVCC 5.25V. Tie to VCC (Pin 8) and bypass with a 1F capacitor to ground. C1 - (Pin 4): Capacitor C1 Negative Terminal. D1 (Pin 5): TTL Level Driver 1 Input. D2 (Pin 6): TTL Level Driver 2 Input. D3 (Pin 7): TTL Level Driver 3 Input. Becomes a CMOS level output when the chip is in the echoed clock mode (EC = 0V). U U U 5 LTC1343 PIN FUNCTIONS VCC (Pin 8): Positive Supply for the Transceivers. 4.75V VCC 5.25V. Tie to PWRVCC (Pin 3). D4 (Pin 9): TTL Level Driver 4 Input. D4EN (Pin 10): TTL Level Enable Input for Driver 4. When high, driver 4 outputs are enabled. When low, driver 4 outputs are forced into a high impedance state. D4EN is not affected by the LATCH pin. INVERT (Pin 11): TTL Level Signal Invert Input. When high, an extra inverter will be added to the driver 4 and receiver 1 signal path. The data stream will change polarity, i.e., a 1 becomes 0 and a 0 becomes a 1. When the pin is low the data flows through with no polarity change. INVERT is not affected by the LATCH pin. R1EN (Pin 12): Logic Level Enable Input for Receiver 1. When low, receiver 1 output is enabled. When high, receiver 1 output is forced into a high impedance state. R1O (Pin 13): CMOS Level Receiver 1 Output. R2O (Pin 14): CMOS Level Receiver 2 Output. R3O (Pin 15): CMOS Level Receiver 3 Output. R4O (Pin 16): CMOS Level Receiver 4 Output. M0 (Pin 17): TTL Level Mode Select Input 0. The data on M0 is latched when LATCH is high. M1 (Pin 18): TTL Level Mode Select Input 1. The data on M1 is latched when LATCH is high. M2 (Pin 19): TTL Level Mode Select Input 2. The data on M2 is latched when LATCH is high. CTRL/CLK (Pin 20): TTL Level Mode Select Input. When the pin is low the chip will be configured for clock and data signals. When the pin is high the chip will be configured for control signals. The data on CTRL/CLK is latched when LATCH is high. DCE/DTE (Pin 21): TTL Level Mode Select Input. When high, the DCE mode is selected. When low the DTE mode is selected. The data on DCE/DTE is latched when LATCH is high. LATCH (Pin 22): TTL Level Logic Signal Latch Input. When low the input buffers on M0, M1, M2, CTRL/CLK, DCE/ DTE, LB and EC are transparent. When LATCH is pulled high the data on the logic pins is latched into their respective input buffers. The data latch allows the logic lines to be shared between multiple I/O ports. LB (Pin 23): TTL Level Loop-Back Select Input. When low the chip enters the loop-back configuration and is configured for normal operation when LB is high. The data on LB is latched when LATCH is high. EC (Pin 24): TTL Level Echoed Clock Select Input. When low the part enters the echoed clock configuration and is configured for normal operation when EC is high. The data on EC is latched when LATCH is high. 423 SET (Pin 25): Analog Input Pin for the RS423 Driver Output Rise and Fall Time Set Resistor. Connect the resistor from the pin to ground. R4 A (Pin 26): Receiver 4 Inverting Input. R3 B (Pin 27): Receiver 3 Noninverting Input. R3 A (Pin 28): Receiver 3 Inverting Input. R2 B (Pin 29): Receiver 2 Noninverting Input. R2 A (Pin 30): Receiver 2 Inverting Input. R1 B (Pin 31): Receiver 1 Noninverting Input. R1 A (Pin 32): Receiver 1 Inverting Input. D4 B (Pin 33): Driver 4 Noninverting Output. D4 A (Pin 34): Driver 4 Inverting Output. D3 B (Pin 35): Driver 3 Noninverting Output. D3 A (Pin 36): Driver 3 Inverting Output. D2 B (Pin 37): Driver 2 Noninverting Output. D2 A (Pin 38): Driver 2 Inverting Output. D1 A (Pin 39): Driver 1 Inverting Output. GND (Pin 40): Signal Ground. Connect to PGND (Pin 41). PGND (Pin 41): Charge Pump Power Ground. Connect to the GND (Pin 40). VEE (Pin 42): Generated Negative Supply Voltage. Connect a 3.3F capacitor to ground. C2 - (Pin 43): Capacitor C2 Negative Terminal. Connect a 1F capacitor between C2 + and C2 -. C2 + (Pin 44): Capacitor C2 Positive Terminal. Connect a 1F capacitor between C2 + and C2 - . 6 U U U LTC1343 TEST CIRCUITS A RL 50 VOD RL 50 B VOC CL 100pF CL 100pF B A B A RL 100 R 15pF 1343 F01 1343 F02 Figure 1. RS422 Driver Test Circuit Figure 2. RS422 Driver/Receiver AC Test Circuit 50 D B VOD A 50 125 VCM 50 125 B A 50 15pF 1343 F03 R Figure 3. V.35 Driver/Receiver Test Circuit D A D CL RL A A R 15pF 1343 F04 1343 F04 Figure 4. V.10/V.28 Driver Test Circuit Figure 5. V.10/V.28 Receiver Test Circuit ODE SELECTIO M2 0 0 0 0 0 1 1 1 1 1 LTC1343 MODE NAME V.10, RS423 EIA-530-A Clock and Data EIA-530-A Control Reserved X.21 V.35 Clock and Data V.35 Control EIA-530, RS449, V.36 V.28, RS232 No Cable U M1 0 0 0 1 1 0 0 0 1 1 M0 0 1 1 0 1 0 0 1 0 1 CTRL/CLK X 0 1 X X 0 1 X X X D1 V.10 V.10 V.10 V.10 V.10 V.28 V.28 V.10 V.28 Z D2 V.10 V.11 V.11 V.11 V.11 V.35 V.28 V.11 V.28 Z D3 V.10 V.11 V.10 V.11 V.11 V.35 V.28 V.11 V.28 Z D4 V.10 V.11 V.11 V.11 V.11 V.35 V.28 V.11 V.28 Z R1 V.10 V.11 V.11 V.11 V.11 V.35 V.28 V.11 V.28 Z R2 V.10 V.11 V.10 V.11 V.11 V.35 V.28 V.11 V.28 Z R3 V.10 V.11 V.11 V.11 V.11 V.35 V.28 V.11 V.28 Z R4 V.10 V.10 V.10 V.10 V.10 V.28 V.28 V.10 V.28 Z W 7 LTC1343 SWITCHI G TI E WAVEFOR S 5V D 0V B-A VO 50% -VO A VO B t SKEW t SKEW 1343 F06 1.5V t PLH 90% 10% tr f = 1MHz : t r 10ns : t f 10ns 1/2 VO Figure 6. V.11, V.35 Driver Propagation Delays VOD2 B-A -VOD2 VOH R VOL 0V t PLH 1.5V Figure 7. V.11, V.35 Receiver Propagation Delays 3V D 0V VO A -VO tf 1.5V t PHL 3V 0V -3V -3V tr 0V 1.5V t PLH 3V 1343 F08 Figure 8. V.10, V.28 Driver Propagation Delays VIH A VIL VOH R VOL 1.3V t PHL 1.7V t PLH 2.4V 0.8V 1343 F09 Figure 9. V.10, V.28 Receiver Propagation Delays 8 W W U 1.5V t PHL VDIFF = V(A) - V(B) 90% tf 50% 10% f = 1MHz : t r 10ns : t f 10ns INPUT 0V t PHL OUTPUT 1.5V 1343 F07 LTC1343 APPLICATIONS INFORMATION Overview The LTC1343 is a 4-driver/4-receiver multiprotocol transceiver that operates from a single 5V supply. Two LTC1343s form the core of a complete software-selectable DTE or DCE interface port that supports the RS232, RS449, EIA-530, EIA-530-A, V.35, V.36 or X.21 protocols. Cable termination may be implemented using the LTC1344 DTE SERIAL CONTROLLER LL LTC1343 D1 LTC1344 LL LTC1344 TXD D2 SCTE D3 D4 TXC R1 RXC R2 RXD R3 TM R4 LTC1343 RL RL D1 RTS D2 DTR D3 D4 DCD R1 DSR R2 CTS RI R3 R4 Figure 10. Complete Multiprotocol Interface in EIA-530 Mode U W U U software-selectable cable termination chip or by using existing discrete designs. A complete DCE-to-DTE interface operating in EIA-530 mode is shown in Figure 10. The first LTC1343 of each port is used to generate the clock and data signals along with LL (Local Loop-back) and TM (Test Mode). The second LTC1343 is used to generate the control signals along with DCE LTC1343 R4 SERIAL CONTROLLER LL TXD 103 R3 TXD SCTE 103 R2 SCTE R1 103 TXC D4 TXC 103 RXC D3 RXC 103 RXD TM D2 RXD D1 TM LTC1343 R4 RL RTS RTS R3 DTR R2 DTR R1 DCD D4 DCD DSR D3 DSR CTS RI D2 CTS D1 RI 1343 F10 9 LTC1343 APPLICATIONS INFORMATION RL (Remote Loop-back) and RI (Ring Indicate). The LTC1344 cable termination chip is used only for the clock and data signals because they must support V.35 cable termination. The control signals do not need any external resistors. Mode Selection The interface protocol is selected using the mode select pins M0, M1, M2 and CTRL/CLK (see the Mode Selection table). The CTRL/CLK pin should be pulled high if the LTC1343 is being used to generate control signals and pulled low if used to generate clock and data signals. For example, if the port is configured as a V.35 interface, the mode selection pins should be M2 = 1, M1 = 0, M0 = 0. For the control signals, CTRL/CLK = 1 and the drivers and receivers will operate in RS232 (V.28) electrical mode. For the clock and data signals, CTRL/CLK = 0 and the drivers and receivers will operate in V.35 electrical mode, except for the single-ended driver and receiver which will operate in the RS232 (V.28) electrical mode. The DCE/DTE pin LATCH LTC1344 DCE/ DTE M2 22 (DATA) LTC1343 M0 20 22 M1 M2 DCE/DTE R1, 10k 17 R2, 10k CTRL/CLK LATCH 18 R3, 10k 19 R4, 10k 21 VCC VCC VCC NC VCC NC CABLE LTC1343 DCE/DTE M2 VCC 20 22 CTRL/CLK LATCH M1 M0 (DATA) 21 19 18 17 1343 F11 M1 M0 (DATA) 24 1 CONNECTOR 23 Figure 11: Single Port DCE/V.35 Mode Selection in the Cable 10 U W U U will configure the port for DCE mode when high, and DTE when low. The interface protocol may be selected simply by plugging the appropriate interface cable into the connector. The mode pins are routed to the connector and are left unconnected (1) or wired to ground (0) in the cable as shown in Figure 11. The pull-up resistors R1 through R4 will ensure a binary 1 when a pin is left unconnected and that the two LTC1343s and the LTC1344 enter the no-cable mode when the cable is removed. In the no-cable mode the LTC1343 supply current drops to less than 200A and all LTC1343 driver outputs and LTC1344 resistive terminations are forced into a high impedance state. Note that the data latch pin, LATCH, is shorted to ground for all chips. The interface protocol may also be selected by the serial controller or host microprocessor as shown in Figure 12. The mode selection pins M0, M1, M2 and DCE/DTE can be shared between multiple interface ports, while each port 21 LTC1343 APPLICATIONS INFORMATION PORT #1 M0 CONNECTOR #1 M1 M2 DCE/DTE LATCH PORT #2 M0 CONNECTOR #2 M1 M2 DCE/DTE CONTROLLER LATCH PORT #3 M0 M1 M2 DCE/DTE LATCH 1 LATCH 2 LATCH 3 M0 CONNECTOR #3 M1 M2 DCE/DTE LATCH 1343 F12 Figure 12: Mode Selection by the Controller has a unique data latch signal which acts as a write enable. When the LATCH pin is low the buffers on the M0, M1, M2, CTRL/CLK, DCE/DTE, LB and EC pins are transparent. When the LATCH pin is pulled high the buffers latch the data and changes on the input pins will no longer affect the chip. The mode selection may also be accomplished by using jumpers to connect the mode pins to ground or VCC. Cable Termination Traditional implementations have included switching resistors with expensive relays, or requiring the user to change termination modules every time the interface standard has changed. Custom cables have been used with the termination in the cable head, or separate terminations are built on the board and a custom cable routes the signals to the appropriate termination. Switching the terminations with FETs is difficult because the FETs must -10V U W U U remain off even though the signal voltage is beyond the supply voltage for the FET drivers or the power is off. Using the LTC1344 along with the LTC1343 solves the cable termination switching problem. Via software control, the LTC1344 provides termination for the V.10 (RS423), V.11 (RS422), V.28 (RS232) and V.35 electrical protocols. V.10 (RS423) Interface A typical V.10 unbalanced interface is shown in Figure 13. A V.10 single-ended generator output A with ground C is connected to a differential receiver with inputs A' connected to A, and input B' connected to the signal return ground C. The receiver's ground C' is separate from the signal return. Usually, no cable termination is required for V.10 interfaces, but the receiver inputs must be compliant with the impedance curve shown in Figure 14. BALANCED INTERCONNECTING CABLE GENERATOR LOAD CABLE TERMINATION RECEIVER A A' C B' C' 1343 F13 Figure 13. Typical V.10 Interface IZ 3.25mA -3V VZ 3V 10V 1343 F14 -3.25mA Figure 14. V.10 Receiver Input Impedance 11 LTC1343 APPLICATIONS INFORMATION The V.10 receiver configuration in the LTC1343 and LTC1344 is shown in Figure 15. In V.10 mode switches S1 and S2 inside the LTC1344 and S3 inside the LTC1343 are turned off. Switch S4 inside the LTC1343 shorts the noninverting receiver input to ground so the B input at the connector can be left floating. The cable termination is then the 30k input impedance to ground of the LTC1343 V.10 receiver. V.11 (RS422) Interface A typical V.11 balanced interface is shown in Figure 16. A V.11 differential generator with outputs A and B with ground C is connected to a differential receiver with ground C', inputs A' connected to A, B' connected to B. The V.11 interface has a differential termination at the receiver end that has a minimum value of 100. The termination resistor is optional in the V.11 specification, but for the high speed clock and data lines, the termination is required to prevent reflections from corrupting the data. The reA' A R1 51.5 S1 S2 R2 51.5 B' LTC1344 R8 6k S3 R5 20k R6 10k RECEIVER S1 S2 R7 10k B' R2 51.5 R3 124 S3 LTC1343 R1 51.5 LTC1344 R3 124 B R4 20k S4 GND C' Figure 15. V.10 Receiver Configuration BALANCED INTERCONNECTING CABLE GENERATOR LOAD CABLE TERMINATION RECEIVER A A' 100 MIN B C B' C' Figure 16. Typical V.11 Interface 12 U W U U ceiver inputs must also be compliant with the impedance curve shown in Figure 14. In V.11 mode, all switches are off except S1 inside the LTC1344 which connects a 103 differential termination impedance to the cable as shown in Figure 17. V.28 (RS232) Interface A typical V.28 unbalanced interface is shown in Figure 18. A. V.28 single-ended generator output A with ground C is connected to a single-ended receiver with inputs A' connected to A, ground C' connected via the signal return ground C. In V.28 mode all switches are off except S3 inside the LTC1343 which connects a 6k (R8) impedance to ground in parallel with 20k (R5) plus 10k (R6) for a combined impedance of 5k as shown in Figure 19. The noninverting input is disconnected inside the LTC1343 receiver and connected to a TTL level reference voltage for a 1.4V receiver trip point. A' A R8 6k R5 20k R6 10k RECEIVER LTC1343 B R4 20k S4 GND R7 10k 1343 F15 C' 1343 F17 Figure 17. V.11 Receiver Configuration BALANCED INTERCONNECTING CABLE GENERATOR LOAD CABLE TERMINATION RECEIVER A A' 1343 F16 C C' 1343 F18 Figure 18. Typical V.28 Interface LTC1343 APPLICATIONS INFORMATION A' A R1 51.5 S1 S2 R2 51.5 B' LTC1344 R8 6k S3 R5 20k R6 10k RECEIVER S1 S2 R4 20k S4 GND R7 10k B' R2 51.5 R3 124 S3 LTC1343 R1 51.5 LTC1344 A' A R8 6k R5 20k R6 10k RECEIVER LTC1343 R3 124 B C' Figure 19. V.28 Receiver Configuration V.35 Interface A typical V.35 balanced interface is shown in Figure 20. A V.35 differential generator with outputs A and B with ground C is connected to a differential receiver with ground C', inputs A' connected to A, B' connected to B. The V.35 interface requires a T or delta network termination at the receiver end and the generator end. The receiver differential impedance measured at the connector must be 100 10, and the impedance between shorted terminals (A' and B) and ground C' must be 150 15. In V.35 mode, both switches S1 and S2 inside the LTC1344 are on, connecting the T network impedance as shown in Figure 21. Both switches in the LTC1343 are off. The 30k input impedance of the receiver is placed in parallel with the T network termination, but does not affect the overall input impedance significantly. BALANCED INTERCONNECTING CABLE GENERATOR LOAD CABLE TERMINATION RECEIVER A 50 A' 50 125 125 50 B C B' 50 C' 1343 F20 Figure 20. Typical V.35 Interface U W U U B R4 20k S4 GND R7 10k 1343 F19 C' 1343 F21 Figure 21. V.35 Receiver Configuration The generator differential impedance must be 50 to 150 and the impedance between shorted terminals (A and B) and ground C must be 150 15. For the generator termination, switches S1 and S2 are both on and the top side of the center resistor is brought out to a pin so it can be bypassed with an external capacitor to reduce common mode noise as shown in Figure 22. Any mismatch in the driver rise and fall times or skew in the driver propagation delays will force current through the center termination resistor to ground, causing a high frequency common mode spike on the A and B terminals. The common mode spike can cause EMI problems that are reduced by capacitor C1 which shunts much of the common mode energy to ground rather than down the cable. A LTC1344 51.5 S1 ON V.35 DRIVER 124 S2 ON 51.5 B C1 100pF C 1343 F22 Figure 22. V.35 Driver Using the LTC1344 13 LTC1343 APPLICATIONS INFORMATION Echoed Clock Mode The LTC1343 contains the logic to generate the echoed clock when using a serial controller with only two clock pins. Figure 23 shows the chip in both the DTE and DCE echoed clock in EIA-530 mode. The control signals are not shown. The echoed clock configuration is selected by pulling the EC pin low. On the DTE side the transmit clock TXC receiver output is connected to the echoed clock, SCTE, driver input. The TXC pin on the serial controller is configured as an input. On the DCE side, the transmit clock from the serial controller is used to generate both TXC and RXC. A phase inverter is placed in the TXC signal path on both the DTE and DCE side to help correct phase problems with long cables. If the Invert pin is high, the phase of the data is inverted. Loop-Back The LTC1343 contains logic for placing the interface into a loop-back configuration for testing. Both DTE and DCE loop-back configurations are supported. Figure 24 shows a complete DTE interface in the loop-back configuration with the EC pin pulled high. The loop-back configuration is selected by pulling the LB pin low. Both the line side and logic side signals are looped back. The DCE loop-back configuration is shown in Figure 25. If the echoed clock mode is selected by pulling EC low, D3 becomes an output and is connected to receiver 2's output R3 in DTE mode as shown in Figure 26. In the echoed clock DCE loop-back mode, driver 4 is connected to driver 3's input D3 as shown in Figure 27. DTE SERIAL CONTROLLER LL LTC1343 D1 LTC1344 LL LTC1344 R4 TXD D2 TXC D3 D4 INVERT R1 103 TXC RXC R2 103 RXD R3 103 TM R4 CTRL/CLK CTRL/CLK DCE/DTE M0 M1 M2 DCE/DTE LATCH M0 M1 M2 DCE/DTE LATCH DCE/DTE LATCH LATCH M0 M1 M2 M0 M1 M2 LB EC LB EC 1 0 1 0 0 1 0 0 10100 Figure 23. EIA-530 Echoed Clock Configuration 14 U W U U DCE LTC1343 SERIAL CONTROLLER LL TXD 103 R3 RXD SCTE 103 R2 RXC R1 INVERT D4 RXC D3 TXC RXD TM D2 TXD D1 TM 1343 F23 10110 1 0 1 0 1 1 0 0 LTC1343 APPLICATIONS INFORMATION SERIAL CONTROLLER LL LTC1343 D1 LTC1344 LL LL LTC1344 R4 LTC1343 SERIAL CONTROLLER LL TXD D2 SCTE D3 D4 TXC R1 103 RXC R2 103 RXD R3 103 TM R4 CTRL/CLK CTRL/CLK DCE/DTE M0 M1 M2 DCE/DTE LATCH M0 M1 M2 DCE/DTE LATCH DCE/DTE LATCH 1 0 1 0 0 0 1 0 10100 1 011 0 1 0 1 0 1 0 1 LTC1343 RL D1 RL RL R4 LTC1343 RL RTS D2 RTS RTS R3 LATCH M0 M1 M2 M0 M1 M2 LB EC LB EC DTR D3 D4 DCD R1 DSR R2 CTS RI R3 R4 CTRL/CLK CTRL/CLK DCE/DTE DCE/DTE LATCH M0 M1 M2 LB EC 1343 F24 LATCH M0 M1 M2 LB EC 1 0 1 1 0 0 1 0 Figure 24. Normal DTE Loop-Back U W U U TXD TXD 103 R3 TXD SCTE SCTE 103 R2 SCTE R1 TXC TXC D4 TXC RXC RXC D3 RXC RXD TM RXD TM D2 RXD D1 TM 0 RTS DTR DTR R2 DTR R1 DCD DCD D4 DCD DSR DSR D3 DSR CTS RI CTS RI D2 D1 CTS RI 1343 F25 1 0 1 1 1 0 1 0 Figure 25. Normal DCE Loop-Back 15 LTC1343 APPLICATIONS INFORMATION SERIAL CONTROLLER LL LTC1343 D1 LTC1344 LL LL LTC1344 R4 LTC1343 SERIAL CONTROLLER LL TXD D2 TXC D3 D4 R1 103 RXC R2 103 RXD R3 103 TM CTRL/CLK DCE/DTE R4 M0 M1 M2 DCE/DTE LATCH CTRL/CLK M0 M1 M2 DCE/DTE LATCH DCE/DTE LATCH 1 0 1 0 0 0 0 0 10100 1 011 0 1 0 1 0 1 0 0 LTC1343 RL D1 RL RL R4 LTC1343 RL RTS D2 RTS RTS R3 LATCH M0 M1 M2 M0 M1 M2 LB EC LB EC DTR D3 D4 DCD R1 DSR R2 CTS RI CTRL/CLK R3 R4 CTRL/CLK DCE/DTE DCE/DTE LATCH M0 M1 M2 LB EC LATCH M0 M1 M2 LB EC 1 0 1 1 0 0 1 0 Figure 26. Echoed Clock, DTE Loop-Back 16 U W U U TXD TXD 103 R3 RXD TXCE SCTE 103 R2 RXC R1 TXC TXC D4 RXC RXC D3 TXC RXD TM RXD TM D2 TXD D1 TM 0 RTS DTR DTR R2 DTR R1 DCD DCD D4 DCD DSR DSR D3 DSR CTS RI CTS RI D2 D1 CTS RI 1343 F26 1 0 1 1 1 0 1 0 1343 F27 Figure 27. Echoed Clock, DCE Loop-Back LTC1343 APPLICATIONS INFORMATION No-Cable Mode The no-cable mode (M0 = M1 = M2 = 1) is intended for the case when the cable is disconnected from the connector. The charge pump, bias circuitry, drivers and receivers are turned off, the driver outputs are forced into a high impedance state, and the supply current drops to less than 200A. It can also be used to share I/O lines with other drivers and receivers without loading down the signals. Charge Pump The LTC1343 uses an internal capacitive charge pump to generate VDD and VEE as shown in Figure 28. A voltage doubler generates about 8V on VDD and a voltage inverter generates about - 7.5V for VEE. Four 1F surface mounted tantalum or ceramic capacitors are required for C1, C2, C3 and C4. The VEE capacitor C5 should be a minimum of 3.3F. All capacitors are 16V. Receiver Fail-Safe and Glitch Filter All LTC1343 receivers feature fail-safe operation in all modes except no-cable mode. If the receiver inputs are left floating or shorted together by a termination resistor, the receiver output will always be forced to a logic high. External pull-up resistors are required on receiver outputs if fail-safe operation in the no-cable mode is desired. When the chip is configured for control signals by pulling the CTRL/CLK pin high, a glitch filter is connected to all receiver inputs. The filter will reject any glitches at the receiver inputs less than 300ns. V.10 Driver Rise and Fall Times The rise and fall times of the V.10 drivers is programmed by placing a 1/8W, 5% resistor between the 423 SET (Pin 25) and ground. The graph of Driver Rise and Fall Times vs Resistor Value is shown in Figure 29. Enabling the Single-Ended Driver and Receiver When the LTC1343 is being used to generate the control signals (CTRL/CLK = high) and the EC pin is pulled low, the DCE/DTE pin becomes an enable for driver 1 and receiver 4 so their inputs and outputs can be tied together as shown in Figure 30. VCC LTC1343 5 DCE/DTE 21 16 20 24 CTRL/CLK EC 1343 F30 4 8 C1- VCC PGND GND 41 40 Figure 28. Charge Pump 100 DRIVER RISE/FALL TIME (s) 10 1 0.1 1k 10k 100k RESISTANCE () 1M 5M 1343 F29 Figure 29. V.10 Driver Rise and Fall Time vs Resistor Value D1 39 R4 26 Figure 30. Single-Ended Driver and Receiver Enable + U W U U 5V + 1 C3 1F 2 C1 1F 3 VDD C1+ LTC1343 PWRVCC C2 + 44 + + + C4 1F 43 C2 - VEE 42 C2 1F C5 3.3F 1343 F28 17 LTC1343 APPLICATIONS INFORMATION The EC pin has no affect on the configuration when CTRL/ CLK is high except to allow the DCE/DTE pin to become an enable. When DCE/DTE is low, the driver 1 output is enabled. The receiver 4 output goes into three-state and the input presents a 30k load to ground. When DCE/DTE is high, the driver 1 output goes into threestate and the receiver 4 output is enabled. The receiver 4 input presents a 30k load to ground in all modes except when configured for RS232 operation when the input impedance is 5k to ground. DTE vs DCE Operation The DCE/DTE pin does not allow a given LTC1343 pin to be reconfigured as a driver or receiver. The DCE/DTE pin only selects the loop-back topology and acts as an enable for the single-ended driver and receiver for control signals. However, the LTC1343 can be configured for either DTE or DCE operation in one of three ways: a dedicated DTE or DCE port with a connector of appropriate gender, a port with one connector that can be configured for DTE or DCE operation by rerouting the signals to the LTC1343 using a dedicated DTE cable or dedicated DCE cable, or a port with one connector and one cable using four LTC1343s. A dedicated DTE port using a DB-25 male connector is shown in Figure 31. The interface mode is selected by logic outputs from the controller or from jumpers to either VCC or GND on the mode select pins. A dedicated DCE port using a DB-25 female connector is shown in Figure 32. A port with one DB-25 connector that can be configured for either DTE or DCE operation is shown in Figure 33. The configuration requires separate cables for proper signal routing in DTE or DCE operation. For example, in DTE mode, the TXD signal is routed to connector Pins 2 and 14 via driver 2 in the LTC1343. In DCE mode, driver 2 now routes the RXD signal to Pins 2 and 14. A combination DTE/DCE port that doesn't require separate DCE/DTE cables is shown in Figure 34. In DTE mode, the top and bottom LTC1343s are enabled and the middle two are placed in the no-cable mode, which forces all of the drivers and receivers into a high impedance state. In the DCE mode, the middle two LTC1343s are enabled and the top and bottom LTC1343s disabled. With this scheme, any connector pin can be configured for sending or receiving signals. Note that only one LTC1344 is required. Multiprotocol Interface with Ring-Indicate and a DB-25 Connector If the RI signal in RS232 mode is implemented, driver 4 and receiver 1 in the control chip can be tied to connector Pin 22 in order to implement the RI signal in RS232 mode and DSR B signal for the other modes. Figure 35 shows the DTE configuration and Figure 36 the DCE configuration. In DCE mode, the DCE/DTE pin should be driven with a logic signal from the controller that goes low only when the interface is in the RS232 mode. Since the receiver 4 input impedance is greater than 30k in all modes except RS232, it can be enabled at all other times and not load down the line. When driver 1 is disabled, it remains in a high impedance state and does not load the line. Cable-Selectable Multiprotocol Interface A cable-selectable multiprotocol DTE/DCE interface is shown in Figure 37. The control signals LL, RL and TM are not implemented. The select lines M0, M1 and DCE/DTE are brought out to the connector. The mode is selected through the cable by wiring M0 (connector Pin 18), M1 (connector Pin 21) and DCE/DTE (connector Pin 25) to ground (connector Pin 7) or letting them float. If M0, M1 or DCE/DTE are floating, pull-up resistors R3, R4 and R5 will pull the signals to VCC. The select bit M1 is hard wired to VCC. When the cable is pulled out, the interface will go into the no-cable mode. Multiprotocol Interface with a DB-26 Connector The controller-selectable multiprotocol DTE/DCE interface with a standard DB-26 connector is shown in Figure 38. The RL, LL and TM signals are implemented and RI is mapped to Pin 26 on the connector. A cable-selectable version is shown in Figure 39. The TM and RL signals have been dropped, but LL is still implemented. 18 U W U U LTC1343 APPLICATIONS INFORMATION C6 100pF C7 100pF C8 100pF 3 VCC 5V 14 VCC 8 11 12 13 LTC1344 21 + 1 C3 1F 44 43 42 41 LTC1343 + C1 1F 2 4 3 8 5 6 7 9 10 12 13 14 15 CHARGE PUMP + C2 1F 2 VEE C4 3.3F 5 4 6 7 9 10 16 15 + LL TXD SCTE C5 1F D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 TXC RXC RXD TM R1 R2 R3 16 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET R1 100k 40 GND 23 LB 1 C11 1F C9 1F DCE 19 M2 18 M1 17 M0 EC 24 VCC + 44 43 42 41 LTC1343 + 2 4 3 8 5 6 7 9 10 12 13 14 15 16 CHARGE PUMP + C10 1F C13 3.3F + C12 1F RL RTS DTR D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 DCE 19 M2 18 M1 17 M0 24 EC DCD DSR CTS R1 R2 R3 VCC LATCH R2 100k LB M2 M1 M0 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 40 GND 23 LB Figure 31: Controller-Selectable Multiprotocol DTE Port with DB-25 Connector + VCC U + W U U LATCH LATCH DCE/ DTE M2 M1 M0 18 17 19 20 22 23 24 1 18 DB-25 MALE CONNECTOR LL A (141) 2 TXD A (103) 14 TXD B 24 SCTE A (113) 11 SCTE B 15 12 17 9 3 16 25 TXC A (114) TXC B RXC A (115) RXC B RXD A (104) RXD B TM A (142) 7 1 SGND (102) SHIELD (101) RL A (140) 4 RTS A (105) 19 RTS B 20 DTR A (108) 23 DTR B 21 8 DCD A (109) 10 DCD B 6 DSR A (107) 22 DSR B 5 CTS A (106) 13 CTS B 1343 F31 19 LTC1343 APPLICATIONS INFORMATION C6 100pF C7 100pF C8 100pF 3 VCC 5V 14 VCC 8 11 12 13 LTC1344 21 + 1 C3 1F C1 1F 44 43 42 41 LTC1343 + 2 4 3 8 5 6 7 9 CHARGE PUMP + C2 1F 2 VEE C4 3.3F 5 4 6 7 9 10 DB-25 FEMALE CONNECTOR 25 3 16 17 9 15 12 VCC 24 SCTE A (113) 11 SCTE B 2 TXD A (103) 14 TXD B 18 LL A (141) VCC C5 1F TM RXD RXC TXC VCC D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 DCE 19 M2 18 M1 17 M0 10 12 13 14 15 R1 R2 R3 SCTE TXD LL 16 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET R1 100k 40 GND 23 LB 1 C11 1F C9 1F EC 24 VCC + 44 43 42 41 LTC1343 + 2 4 3 8 5 6 7 9 CHARGE PUMP VCC + C12 1F D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 DCE 19 M2 18 M1 17 M0 5 13 6 22 8 10 CTS A (106) CTS B DSR A (107) DSR B DCD A (109) DCD B CTS DSR DCD VCC 10 12 13 14 15 16 R1 R2 R3 DTR CTS RL VCC LATCH R2 100k LB M2 M1 M0 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET VCC 1343 F32 40 GND 23 LB EC 24 Figure 32: Controller-Selectable Multiprotocol DCE Port with DB-25 Connector 20 + + + + C10 1F C13 3.3F U W U U LATCH LATCH DCE/ DTE M2 M1 M0 16 15 18 17 19 20 22 23 24 1 TM A (142) RXD A (104) RXD B RXC A (115) RXC B TXC A (114) TXC B 7 SGND (102) 1 SHIELD (101) 20 DTR A (108) 23 DTR B 4 RTS A (105) 19 RTS B 21 RL A (140) LTC1343 APPLICATIONS INFORMATION C6 100pF C7 100pF C8 100pF 3 VCC 5V 14 VCC 8 11 12 13 LTC1344 21 + 1 C3 1F + C1 1F C5 1F 2 4 3 8 LTC1343 5 6 7 9 10 12 13 14 15 D1 D2 D3 D4 CHARGE PUMP 41 DTE_LL/DCE_TM DTE_TXD/DCE_RXD DTE_SCTE/DEC_RXC 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 DCE 19 M2 18 M1 17 M0 DTE_TXC/DCE_TXC DTE_RXC/DCE_SCTE DTE_RXD/DCE_TXD DTE_TM/DCE_LL R1 R2 R3 R1 100k 16 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 40 GND 23 LB 1 EC 24 + 44 43 42 41 LTC1343 C11 1F C9 + 2 4 3 8 5 6 7 9 10 12 13 14 15 16 CHARGE PUMP + C10 1F C13 3.3F 1F VCC + C12 1F DTE_RL/DCE_RL DTE_RTS/DCE_CTS DTE_DTR/DCE_DSR D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 DCE 19 M2 18 M1 17 M0 DTE_DCD/DCE_DCD DTE_DSR/DCE_DTR DTE_CTS/DCE_RTS R1 R2 R3 VCC LATCH R2 100k LB DCE/DTE M2 M1 M0 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 40 GND 23 LB EC 24 Figure 33. Controller-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector + + + U 44 43 42 W U U LATCH LATCH + C2 1F 2 VEE C4 3.3F 5 4 6 7 9 10 16 15 DCE/ DTE M2 M1 M0 18 17 19 20 22 23 24 1 18 DB-25 CONNECTOR DTE LL A DCE TM A RXD A RXD B RXC A RXC B 2 TXD A 14 TXD B 24 SCTE A 11 SCTE B 15 12 17 9 3 16 TXC A TXC B RXC A RXC B RXD A RXD B TXC A TXC B SCTE A SCTE B TXD A TXD B LL A 25 TM A VCC 7 1 SGND SHIELD RL A 4 RTS A 19 RTS B 20 DTR A 23 DTR B 21 RL A CTS A CTS B DSR A DSR B 8 DCD A 10 DCD B 6 DSR A 22 DSR B 5 CTS A 13 CTS B DCD A DCD B DTR A DTR B RTS A RTS B 1343 F33 21 LTC1343 APPLICATIONS INFORMATION LTC1343 5 6 7 21 DCE 9 10 12 13 14 15 16 R1 R2 R3 R4 LTC1343 TM RXD RXC TXC VCC 5 6 7 21 DCE 9 10 12 13 14 15 16 D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 3 16 17 9 15 12 TM A (142) RXD A (104) RXD B RXC A (115) RXC B TXC A (114) TXC B D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 5 26 DCE/DTE DB-25 CONNECTOR 4 6 7 9 10 16 15 DCE/ DTE 18 17 19 20 22 C6 100pF C7 100pF C8 100pF 3 8 11 12 13 R1 R2 R3 R4 LTC1343 SCTE TXD LL 5 6 7 21 DCE 9 10 12 13 14 15 16 D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 26 5 13 6 22 8 10 1 CTS A (106) CTS B DSR A (107) DSR B DCD A (109) DCD B SHIELD (101) CTS DSR VCC DCD R1 R2 R3 R4 LTC1343 DTR RTS RL 5 6 7 21 DCE 9 10 12 13 14 15 16 D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 26 R1 R2 R3 R4 Figure 34. Controller-Selectable Multiprotocol DTE/DCE Port with DB-25 22 U W U U LTC1344 24 SCTE A (113) 11 SCTE B 2 TXD A (103) 14 TXD B 18 LL A (141) 7 SGND (102) 20 DTR A (108) 23 DTR B 4 RTS A (105) 19 RTS B 21 RL A (140) 1343 F34 LTC1343 APPLICATIONS INFORMATION C6 100pF C7 100pF C8 100pF 3 VCC 5V 14 VCC 8 11 12 13 LTC1344 21 + 1 C3 1F C1 1F 44 43 42 41 LTC1343 + 2 4 3 8 5 6 7 9 10 12 13 14 15 CHARGE PUMP + C2 1F 2 VEE C4 3.3F 5 4 6 7 9 10 16 15 + LL TXD SCTE C5 1F D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 TXC RXC RXD TM R1 R2 R3 R1 100k 16 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 40 GND 23 LB 1 DCE 19 M2 18 M1 17 M0 EC 24 VCC + 44 43 42 41 LTC1343 C11 1F C9 1F + 2 4 3 8 5 6 7 9 10 12 13 14 15 16 CHARGE PUMP + C10 1F C13 3.3F + C12 1F RL RTS DTR D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 26 DCE 21 DCD DSR CTS RI VCC LATCH R1 R2 R3 R2 100k LB M2 M1 M0 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 19 M2 18 M1 17 M0 24 40 GND 23 LB EC VCC Figure 35. Controller-Selectable Multiprotocol DTE Port with RI and DB-25 Connector + VCC U + W U U LATCH LATCH DCE/ DTE M2 M1 M0 18 17 19 20 22 23 24 1 18 DB-25 MALE CONNECTOR LL A (141) 2 TXD A (103) 14 TXD B 24 SCTE A (113) 11 SCTE B 15 12 17 9 3 16 25 TXC A (114) TXC B RXC A (115) RXC B RXD A (104) RXD B TM A (142) 7 SGND (102) 1 SHIELD (101) RL A (140) 4 RTS A (105) 19 RTS B 20 DTR A (108) 23 DTR B 21 8 DCD A (109) 10 DCD B 6 DSR A (107) 22 DSR B/RI A (125) 5 CTS A (106) 13 CTS B 1343 F35 23 LTC1343 APPLICATIONS INFORMATION C6 100pF C7 100pF C8 100pF 3 VCC 5V 14 VCC 8 11 12 13 LTC1344 21 + 1 C3 1F C1 1F 44 43 42 41 LTC1343 + 2 4 3 8 5 6 7 9 CHARGE PUMP + C2 1F 2 VEE C4 3.3F 5 4 6 7 9 10 + TM RXD RXC TXC VCC C5 1F D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 DCE 19 M2 18 M1 17 M0 VCC 10 12 13 14 15 R1 R2 R3 SCTE TXD LL R1 100k 16 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 40 GND 23 LB 1 VCC EC 24 VCC + 44 43 42 41 LTC1343 C11 1F + C9 1F C12 1F 2 4 3 8 5 6 7 9 CHARGE PUMP + C10 1F C13 3.3F VCC + RI CTS DSR DCD VCC D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 DCE 19 M2 18 M1 17 M0 RIEN = RS232 1343 F36 10 12 13 14 15 16 R1 R2 R3 DTR CTX RL VCC LATCH R2 100k LB M2 M1 M0 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 40 GND 23 LB EC 24 Figure 36. Controller-Selectable Multiprotocol DCE Port with RI and DB-25 Connector 24 U + + W U U LATCH LATCH DCE/ DTE M2 M1 M0 16 15 18 17 19 20 22 23 24 1 25 3 16 17 9 15 12 DB-25 FEMA;E CONNECTOR TM A (142) RXD A (104) RXD B RXC A (115) RXC B TXC A (114) TXC B 24 SCTE A (113) 11 SCTE B 2 TXD A (103) 14 TXD B 18 LL A (141) 7 1 SGND (102) SHIELD (101) 5 13 6 22 8 10 CTS A (106) CTS B DSR A (107) DSR B/RI A (125) DCD A (109) DCD B 20 DTR A (108) 23 DTR B 4 RTS A (105) 19 RTS B 21 RL A (140) LTC1343 APPLICATIONS INFORMATION C6 100pF C7 100pF C8 100pF 3 VCC 5V 14 VCC 8 11 12 13 LTC1344 21 + 1 C3 1F 44 43 42 41 LTC1343 + C1 1F C5 1F 2 4 3 8 5 6 7 9 10 12 13 14 15 CHARGE PUMP + D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 DCE 19 M2 18 M1 17 M0 VCC DTE 2 TXD A 14 TXD B 24 SCTE A 11 SCTE B DCE RXD A RXD B RXC A RXC B DTE_TXD/DCE_RXD DTE_SCTE/DEC_RXC DTE_TXC/DCE_TXC DTE_RXC/DCE_SCTE DTE_RXD/DCE_TXD R1 R2 R3 R1 100k 16 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 40 GND 23 LB 1 VCC 1 EC 24 VCC + 44 43 42 41 LTC1343 C11 1F C9 1F + 2 4 3 8 5 6 7 9 10 12 13 14 15 16 CHARGE PUMP VCC + C12 1F D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 DCE 19 M2 18 M1 17 M0 4 RTS A 19 RTS B 20 DTR A 23 DTR B CTS A CTS B DSR A DSR B DTE_RTS/DCE_CTS DTE_DTR/DCE_DSR DTE_DCD/DCE_DCD DTE_DSR/DCE_DTR DTE_CTS/ DCE_RTS R1 R2 R3 VCC R2 100k LB R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET VCC 40 GND 23 LB 24 EC Figure 37. Cable-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector + + U W U U LATCH + C2 1F 2 VEE C4 3.3F 5 4 6 7 9 10 16 15 DB-25 CONNECTOR DCE/ DTE M2 M1 M0 18 17 19 20 22 23 24 1 15 12 17 9 3 16 TXC A TXC B RXC A RXC B RXD A RXD B TXC A TXC B SCTE A SCTE B TXD A TXD B 7 SGND SHIELD + C10 1F C13 3.3F VCC R3 10k VCC R4 10k VCC R5 10k 25 21 18 DCE/DTE M1 M0 8 DCD A 10 DCD B 6 DSR A 22 DSR B 5 CTS A 13 CTS B DCD A DCD B DTR A DTR B RTS A RTS B 1343 F37 CABLE WIRING FOR MODE SELECTION MODE PIN 18 PIN 21 V.35 PIN 7 PIN 7 EIA-530, RS449, NC PIN 7 V.36, X.21 RS232 PIN 7 NC CABLE WIRING FOR DTE/DCE SELECTION MODE PIN 25 DTE PIN 7 DCE NC 25 LTC1343 APPLICATIONS INFORMATION C6 100pF C7 100pF C8 100pF 3 VCC 5V 14 VCC 8 11 12 13 LTC1344 21 + 1 C3 1F C1 1F 44 43 42 41 LTC1343 + 2 4 3 8 5 6 7 9 10 12 13 14 15 CHARGE PUMP C5 1F DTE_LL/DCE_TM DTE_TXD/DCE_RXD DTE_SCTE/DEC_RXC D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 DCE 19 M2 18 M1 17 M0 DTE_TXC/DCE_TXC DTE_RXC/DCE_SCTE DTE_RXD/DCE_TXD DTE_TM/DCE_LL R1 R2 R3 R1 100k 16 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 40 GND 23 LB 1 EC 24 + 44 43 42 41 LTC1343 C11 1F + + C9 C12 1F 2 4 3 8 5 6 7 9 10 12 13 14 15 16 CHARGE PUMP 1F VCC + DTE_RL/DCE_RI DTE_RTS/DCE_CTS DTE_DTR/DCE_DSR D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 DCE 19 M2 18 M1 17 M0 DTE_DCD/DCE_DCD DTE_DSR/DCE_DTR DTE_CTS/DCE_RTS DTE_RI/DCE_RL VCC LATCH R1 R2 R3 R2 100k LB DCE/DTE M2 M1 M0 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 40 GND 23 LB EC 24 Figure 38. Controller-Selectable Multiprotocol DTE/DCE Port with DB-26 Connector 26 + + + U W U U LATCH LATCH + C2 1F 2 VEE C4 3.3F 5 4 6 7 9 10 16 15 DB-26 CONNECTOR DCE/ DTE M2 M1 M0 18 17 19 20 22 23 24 1 18 DTE LL A DCE TM A RXD A RXD B RXC A RXC B 2 TXD A 14 TXD B 24 SCTE A 11 SCTE B 15 12 17 9 3 16 TXC A TXC B RXC A RXC B RXD A RXD B TXC A TXC B SCTE A SCTE B TXD A TXD B LL A 25 TM A VCC 7 1 SGND SHIELD C10 1F C13 3.3F RL A 4 RTS A 19 RTS B 20 DTR A 23 DTR B 21 RI A CTS A CTS B DSR A DSR B 8 DCD A 10 DCD B 6 DSR A 22 DSR B 5 CTS A 13 CTS B 26 RI A DCD A DCD B DTR A DTR B RTS A RTS B RL A 1343 F38 VCC LTC1343 APPLICATIONS INFORMATION C6 100pF C7 100pF C8 100pF 3 VCC 5V 14 VCC 8 11 12 13 LTC1344 21 + 1 C3 1F C1 1F 44 43 42 41 LTC1343 + 2 4 3 8 5 6 7 9 10 12 13 14 15 CHARGE PUMP C5 1F D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 DCE 19 M2 18 M1 17 M0 VCC DTE 2 TXD A 14 TXD B 24 SCTE A 11 SCTE B DCE RXD A RXD B RXC A RXC B DTE_TXD/DCE_RXD DTE_SCTE/DEC_RXC DTE_TXC/DCE_TXC DTE_RXC/DCE_SCTE DTE_RXD/DCE_TXD R1 R2 R3 R1 100k 16 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 40 GND 23 LB 1 VCC 1 EC 24 VCC + 44 43 42 41 LTC1343 C11 1F + C9 1F + 2 4 3 8 5 6 7 9 10 12 13 14 15 16 CHARGE PUMP + C12 1F DTE_LL/DCE_LL DTE_RTS/DCE_CTS DTE_DTR/DCE_DSR D1 D2 D3 D4 39 38 37 36 35 34 33 32 31 30 29 28 27 26 21 DCE 19 M2 18 M1 17 M0 4 RTS A 19 RTS B 20 DTR A 23 DTR B CTS A CTS B DSR A DSR B DTE_DCD/DCE_DCD DTE_DSR/DCE_DTR DTE_CTS/DCE_RTS R1 R2 R3 VCC R2 100k LB R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET VCC 1343 F39 40 GND 23 LB 24 EC Figure 39. Cable-Selectable Multiprotocol DTE Port with DB-26 Connector Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. + VCC + + U W U U LATCH + C2 1F 2 VEE C4 3.3F 5 4 6 7 9 10 16 15 DB-26 CONNECTOR DCE/ DTE M2 M1 M0 18 17 19 20 22 23 24 1 15 12 17 9 3 16 TXC A TXC B RXC A RXC B RXD A RXD B TXC A TXC B SCTE A SCTE B TXD A TXD B 7 SGND SHIELD VCC C10 1F C13 3.3F R3 10k VCC R4 10k VCC R5 10k 25 21 18 DCE/DTE M1 M0 8 DCD A 10 DCD B 6 DSR A 22 DSR B 5 CTS A 13 CTS B 26 LL B DCD A DCD B DTR A DTR B RTS A RTS B LL B CABLE WIRING FOR MODE SELECTION MODE PIN 18 PIN 21 V.35 PIN 7 PIN 7 EIA-530, RS449, NC PIN 7 V.36, X.21 RS232 PIN 7 NC CABLE WIRING FOR DTE/DCE SELECTION MODE PIN 25 DTE PIN 7 DCE NC 27 LTC1343 PACKAGE DESCRIPTION U Dimensions in inches (millimeters) unless otherwise noted. GW Package 44-Lead Plastic SSOP (Wide 0.300) (LTC DWG # 05-08-1642) 17.805 - 18.059* (0.701 - 0.711) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 10.160 - 10.414 (0.400 - 0.410) 7.417 - 7.595** (0.292 - 0.299) 0.254 - 0.406 x 45 (0.010 - 0.016) 0 - 8 TYP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2.463 - 2.641 (0.097 - 0.104) 2.286 - 2.387 (0.090 - 0.094) 0.231 - 0.3175 (0.0091 - 0.0125) 0.610 - 1.016 (0.024 - 0.040) 0.800 (0.0315) BSC 0.304 - 0.431 (0.012 - 0.017) 0.127 - 0.292 (0.005 - 0.0115) NOTE: DIMENSIONS ARE IN MILLIMETERS *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE SHALL NOT EXCEED 0.152mm (0.006") PER SIDE G44 SSOP 1098 RELATED PARTS PART NUMBER LTC1321 LTC1334 LTC1344/LTC1344A LTC1345 LTC1346A LTC1543 LTC1544 LTC1545 DESCRIPTION Dual RS232/RS485 Transceiver Single 5V RS232/RS485 Multiprotocol Transceiver Software-Selectable Cable Terminator Single Supply V.35 Transceiver Dual Supply V.35 Transceiver Software-Selectable Multiprotocol Transceiver Software-Selectable Multiprotocol Transceiver Software-Selectable Multiprotocol Transceiver COMMENTS 2 RS232 Driver/Receiver Pairs or 2 RS485 Driver/Receiver Pairs 2 RS232 Driver/Receiver or 4 RS232 Driver/Receiver Pairs Perfect for Terminating the LTC1343 3 Driver/3 Receiver for Data and Clock Signals 3 Driver/3 Receiver for Data and Clock Signals 3 Driver/3 Receiver for Data and Clock Signals 4 Driver/4 Receiver for Control Signals Including LL 5 Driver/5 Receiver for Control Signals Including LL, RL, TM 28 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com 1343fa LT/TP 0899 2K REV A * PRINTED IN USA (c) LINEAR TECHNOLOGY CORPORATION 1996 This datasheet has been downloaded from: www..com Datasheets for electronic components. |
Price & Availability of LTC1343CGW
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |